1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same, and more particularly to a semiconductor device which includes a plurality of core chips and an interface chip for controlling the same and an information processing system which includes the semiconductor device.
2. Description of Related Art
DRAM (Dynamic Random Access Memory) as a typical semiconductor memory device, is usually used in the form of a memory module where a plurality of chips are mounted on a module substrate. FIG. 18 is a schematic diagram for explaining the connection between a memory module and a controller. In the shown example, a memory module composed of two ranks 904a and 904b is connected to a controller 902. The two ranks 904a and 904b belong to rank 1 and rank 2, respectively, and are exclusively activated by respective corresponding chip select signals CS1 and CS2.
Each rank includes eight 2-Gbit DRAM chips 900 (900A to 900H). The memory capacity per rank is thus 16 Gbits, and the system has a total memory capacity of 32 Gbits. Each DRAM chip 900 has eight data input-output terminals DQ, so that 64 bits of data is input/output between the ranks 904a and 904b and the controller 902 at a time. Data wiring for transmitting and receiving such 64 bits of data is connected to rank 1 (904a) and rank 2 (904b) in common.
Similarly, command and address wiring for supplying an address ADD, command CMD, and bank address BA from the controller 902 to the two ranks 904a and 904b is also connected to rank 1 (904a) and rank 2 (904b) in common. Consequently, the same address, command, and bank address are supplied from the controller 902 to the two ranks 904a and 904b. Which of the ranks the addresses and command are enabled in is identified by the chip select signals CS1 and CS2.
FIG. 19 is a schematic diagram for explaining the bank configuration of rank 1 (904a) which is activated by the chip select signal CS1.
As shown in FIG. 19, the eight DRAM chips 900A to 900H that constitute rank 1 (904a) each have eight banks including banks 0 to 7. The banks are units that can accept commands independently. When a bank is executing a predetermined command, a new command can be issued to another bank. The banks are specified by the foregoing bank address.
The address ADD, command CMD, and bank address BA (BA2 to BA0) are supplied to the DRAM chips 900A to 900H in common. For example, when in a read operation, eight bits of read data is read from each memory cell to which the same address is assigned, in each bank to which the same bank address is assigned. As a result, a total of 64 bits of read data is output to the controller 902. The entire address space of rank 1 (904a) is thus the same as that of a single DRAM chip.
Meanwhile, demands on DRAM memory capacity are increasing year by year. In order to meet the demands, there has been proposed a memory device called multi-chip package which includes a plurality of memory chips stacked on each other. A memory chip typically includes a so-called front end unit which provides an interface with outside (such as a memory controller). The available area that can be allocated for memory cores in a memory chip is limited to the total chip area minus the footprint of the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor memory device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural memory chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each memory chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural memory chips (core chips) can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
For example, instead of the eight DRAM chips 900A to 900H shown in FIG. 19, a semiconductor device including a stack of eight core chips and one interface chip can be used to obtain the same memory capacity as that of rank 1 (904a) in a single package. In such a configuration, it is not the case, as with rank 1 (904a), that pieces of data read from the respective DRAM chips are output to the controller 902 in parallel. Instead, any one of the core chips is selected and a piece of data read from the selected core chip is output to the controller 902 through the interface chip. The address space is thus extended eightfold as compared to a single DRAM chip.
Even with the eightfold address space, the number of banks that appear to the controller 902 is still eight. The memory access efficiency is therefore little improved despite the increased memory capacity per package.